The Name Outlives the Register
The Name Outlives the Register
A program names thirty-two registers and believes that is all there is. The hardware knows better. Underneath the fixed architectural names runs a much larger, anonymous pool of physical storage, and every instruction that writes a register is secretly given a fresh, private slot to write into. The name in the instruction stream is a label, reused endlessly; the value behind it is never overwritten while anything still needs the old one. A second write to the same register does not erase the first — it retires the first, once every reader has finished, and moves the name on to point somewhere new.
This is what makes out-of-order execution possible without corrupting meaning. Two instructions can race ahead, write what looks like the same destination, execute in whatever sequence the operands become ready, and still produce a program that behaves as if it ran in the order it was written — because the false hazards, write-after-write and write-after-read, were never real conflicts on the physical hardware, only accidents of a naming scheme that ran out of names. Rename the destinations and the accidents disappear; only the true dependencies, the ones where a value is actually needed, remain to constrain the schedule.
The reorder buffer is the ledger that makes this survivable at the boundary with the outside world. Instructions may finish computing in any order the execution units allow, but they retire — commit their renamed result back into the architectural, visible state — strictly in program order, one at a time, at the head of the buffer. An exception partway through simply stops that commit pointer; everything younger is discarded as if it never happened, because in the only state anyone else can see, it never did.
Speed came from admitting that "register 5" was never a place. It was always a name, temporarily assigned to whichever physical slot currently holds the truth, and the machine runs faster the moment it stops pretending otherwise.
Seed: RISC-V ISA / Out-of-Order Superscalar Microarchitecture — register renaming via Reorder Buffer (ROB) / Unified Register File.